- Liittynyt
- 27.10.2018
- Viestejä
- 206
Eikai nuo 1080ti enää ole suuremman dagin takia vetäneet tuota 53mh muutenkaan pitkään aikaan, max pienen hetken ja sitten tipahtaa sinne 40-45 tasolle. Jotenkin tuo dagin suurentuminen on tuon aiheuttanut vaikka muistia kortissa olisikin riittävästi.. Oma rog strix 1080ti oc vetelee n. 42mh maltillisilla kelloilla, mutta esim eth classiccia 53..
Koita laittaa 70-75% tdp, muistia ei tarvi ainakaan itsellä kellottaa, saa olla vaikka -502 afterburnerissa. Core vaikuttaa sitten herkästi, pidän sitä jossain +150-200 välillä (saattaa olla mallista riippuva, en tiedä kun on vain 1). Tuo rog strix harppaa enemmän virtaa yleisesti niin siinä joutuu tuo tdp olla pari prosenttia enemmän (ei aina).
Blockchain drivers
too bad… got a few cards that are suffering from the problem… and increasing the power to compensate ain’t great… expensive eletric…NVIDIA… HELLO???
forums.developer.nvidia.com
here is a comment from the developer of the miner about this problem:
This is a long-standing problem with Nvidia 10x0 cards. As it started above certain size of DAG and gradually lowers the hashrate with each new epoch, it seems to be related to the TLB size. At this point the only workaround is to increase the power limit (and thus indirectly the core clock) but whether it is worth it depends on your electricity prices. We are testing some theoretical fixes for this problem but the results are not very encouraging. Nvidia could probably fix this with driver update by increasing the page size as AMD did in the past but it is not very likely that they will bother to do it.
I would like to hear a response from NVIDIA
Nvidia
Robert_CrovellaModerator
Aug 11 '20
Here is the reply. Please note that I likely will not be able to respond to any follow-up questions about this. Therefore, if you ask a question, and I do not respond, that is the reason. I’m not permitted to share any more details than what is presented here:
We’ve confirmed that the performance drop is due to the size of the DAG exceeding the total on-chip TLB capacity on the Pascal GPU. As a result, there is an increased number of TLB misses, which affects performance. Because the TLB is a fixed capacity hardware resource, and the ETH algorithm accesses the DAG randomly, we don’t believe there are any software optimizations that could reduce the TLB miss rate.
In the Volta generation, TLB coverage was increased by 4x, and large DAG sizes (up to ~8GB, which won’t be reached for many years) will still fit in the on-chip TLB. So these newer GPUs (Volta and beyond) will show much less performance sensitivity due to DAG size.
TLB = A translation lookaside buffer (TLB) is a memory cache that is used to reduce the time taken to access a user memory location. It is a part of the chip's memory-management unit (MMU). The TLB stores the recent translations of virtual memory to physical memory and can be called an address-translation cache.